For a PLL with discrete frequency calibration points, the gain Kvco (frequency change vs. voltage change) and frequency coverage range of the PLL's Voltage Control Oscillator (VCO) vary significantly with process and voltage variations, such that each adjacent frequency tuning range may not overlap with each other (dead frequency zone). The PLL will fail to lock at the frequencies in the dead frequency zone. Also, a PLL having a high Kvco passes through input clock jitter and degrades the overall PLL noise/jitter performance.